| User Papers |
| MA1 - Coverage |
CovVise: How We Stopped Throwing Away Interesting Coverage Data
Author(s): Wilson Snyder [Veripool.org], Robert Woods-Corwin [NVIDIA] |
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Jazz Up Your Coverage Reports with VMM Planner
Author(s): John Stiles [Silicon Logic Engineering] |
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| MA2 - XA |
LSI Transistor-Level Verification Using XA
Author(s): Amy Rittenhouse, Jianjun Liu, Richard Stephani, Andrew Cable [LSI Corp.] |
|
XA Verification in Implantable Medical Design (1st Place - Best Paper)
Author(s): Garrett Marshall, Jalpa Shah, Scott Stanslaski [Medtronic], Joseph Perttu [Synopsys] |
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| MA3 - Easier Design Closure Using DC and DCT |
RTL Structural Analysis Using Design Compiler (Technical Committee Award)
Author(s): Pete Nixon, Paul Rotker, Matt Cohen, Keith Morse, Bandish Shah [Sun Microsystems] |
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Stop Being Passive - Be Active with DCT
Author(s): Christopher Krueger [STMicroelectronics], Alex Fatehali [Synopsys, Inc.] |
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| MA4 - ICC Usage |
Predictable and Repeatable Feedthrough Floorplanning Using ICC (Technical Committee Award Honorable Mention)
Author(s): Franklin Bodine, Chris McGlone, Duane Galbi [Intel Corp.] |
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The Benefits of MCMM with Multi-Corner Timing Closure
Author(s): Tim Houlihan [Cypress Semiconductor] |
|
| MB1 -SystemVerilog & VMM |
Building a Best Practice VMM Interface VIP Template
Author(s): Ning Guo, Jeff Wilcox, Rich Musacchio [Paradigm Works] |
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E To SystemVerilog Conversion (Technical Committee Award Honorable Mention)
Author(s): Premkishore Shivakumar [Intel Corp.], Alex Wakefield, Jason Chen [Synopsys, Inc.] |
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SystemVerilog's Virtual World - An Introduction to Virtual Classes, Virtual Methods and Virtual Interface Instances (2nd Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.], Heath Chambers [HMC Design Verification, Inc.] |
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| MB2 - HSPICE and HSIM |
How to Get Maxwell and Kirchhoff to Shake Hands Using HSIM/WaveView for EMI Analysis
Author(s): Cornelia Golovanov [LSI Corp.], Cheung Lam [Synopsys] |
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HSPICE Aided S-Parameter Embedding and De-Embedding for High Speed Interface Compliance Testing
Author(s): Johann Nittmann, Frank Corcoran [Cavium Networks] |
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Multi-Gigabit Serial Link Analysis Using HSPICE and AMI Models (3rd Place - Best Paper)
Author(s): Douglas Burns, Barry Katz, Walter Katz, Mike Steinberger, Todd Westerhoff [SiSoft] |
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| MB4 - ICC and IC Validator |
Design Rule Check Classification System with IC Validator (Best First-Time Presenter)
Author(s): Pavel Rott [Intel Corp.] |
|
| MB6 - Test |
Breaking the Hierarchy Rules: An Advanced Hierarchical DFT Strategy for a 5 Million Flop Design
Author(s): Charles Njinda [Cisco Systems] |
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Small-Delay Defect Testing of a High-Volume Server
Author(s): Francisco Duran-Urrea [Advanced Micro Devices], Don Skinner [Synopsys, Inc.] |
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Testing Latch Dominated Designs from a Mixed-Signal and Low-Power Domain
Author(s): Richard Illman, Hans Martin von Staudt [Dialog Semiconductor] |
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| MC1 Simulation and Testbenches |
Accelerating Simulation Performance using VCS in a CPU/GPU Integrated Verification Environment
Author(s): Sonu Arora, Madhuri Nallapaneni, Alex Miretsky, Peter Chi Wing Ng [Advanced Micro Devices] |
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Innovative Testbench Approach for Multi-ASIC Simulation
Author(s): Martin Blouin [Cisco Systems] |
|
| MC3 - Agile Programming and MVSIM |
A Giant, Baby Step Forward: Agile Techniques for Hardware Design
Author(s): Neil Johnson, Bryan Morris [XtremeEDA Corp.] |
|
Low-Power Verification of Multi-Rail Cells in RTL
Author(s): Ramanan Balakrishnan, Borhan Roohipour, Balakrishnamohan Kanukollu [Advanced Micro Devices], Vikram Malik, Tushar Parikh [Synopsys, Inc.] |
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| MC4 - Zroute and IC Compiler |
To Z or not to Z
Author(s): Jeff Shi [LSI Corp.] |