Learn how Formality utilizes powerful links with Design Compiler that enable you to achieve maximum Quality of Results (QoR) while maintaining verifiability.
Joe Bosia, Corporate Applications Engineer, Synopsys
May 03, 2012

Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.
Mark Patton, Product Marketing Director, Synopsys; David Low, Corporate Applications Engineer, Synopsys
Oct 27, 2011

Learn from the expert how to successfully complete low power EC faster, and quickly address verification issues, with UPF in Formality.
Bob Hatt, Corporate Applications Engineer, Synopsys
Mar 15, 2011

This webinar will address what to do when faced with an inconclusive for non-equivalent design in Formality. Common types of failures will be discussed as well as suggestions for resolving them. New features in Formality 2010.03 will be presented which help the designer quickly identify the sources of the issue and makes recommendations on how to resolve them. Recent Formality low power enhancements will also be discussed.
Mitch Milner, R&D Group Director of Formal Verification
Jun 24, 2010

Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.
Krishna Balachandran, Director of Product Marketing, Synopsys; Prapanna Tiwari, Staff CAE, Synopsys; Bob Hatt, Staff CAE, Synopsys
Apr 28, 2010

Join us for an in-depth technical webinar focused on how to achieve successful verification on high-performance designs compiled with DC Ultra.
Mitchell Mliner, Synopsys
Apr 21, 2009