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Synopsys offers designers a broad portfolio of complete, silicon-proven IP solutions for the most widely used interfaces such as PCI Express USB, DDR, SATA, HDMI, MIPI, and Ethernet. With a strong investment in developing high quality IP, designers can trust that the IP will interoperate and integrate successfully into the SoC with less risk and improved time to market.
- AMBA
| Comprehensive IP solutions for AMBA 3 AXI and AMBA 2.0 Protocols | more |
| Infrastructure/Fabric | The DesignWare IP solutions for the AMBA® interconnect includes synthesizable IP, verification IP and an automated method for subsystem assembly. |
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| DMA Controller | The highly optimized centralized DMA Controller supports up to 8 channels each with dedicated channel buffers. |
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| DDR/SDRAM/SRAM Memory Controller | The multi-purpose memory controller supports a wide variety of standard memory devices and provides flexible configuration options. |
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| APB General Peripheral | The highly configurable APB general peripherals provide designers with the flexibility to tailor the components to the desired design requirements. |
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| APB Advanced Peripheral | The highly configurable APB Advanced Peripheral provide designers with the flexibility to tailor the components to their desired design requirements |
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| Verification IP | Synopsys provides designers with the broadest portfolio of verification IP supporting the most popular bus protocols.  DOWNLOAD DATASHEET |
- DDRn
| Comprehensive DDR3, DDR2, DDR IP, Supporting up to 2133 Mbps | more |
| DDR Complete Solution | Complete DDR IP solution consisting of protocol and memory controllers, PHY IP and Verificaiton IP. |
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| Universal DDR Controllers |
Low-latency, area efficient controllers supporting DDR2/DDR3/mDDR/LPDDR2 |
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| DDR2 Protocol Controller | Low latency, area efficient digital interface between a single on-chip interface and a DDR2/DDR PHY. Enables custom scheduler, arbitration and application ports DOWNLOAD DATASHEET |
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| DDR2/3-Lite Protocol Controller | Low latency, area efficient digital interface between a single on-chip interface and a DDR2/DDR, DDR2/3-Lite or DDR2/3-Lite/mDDR PHY. Enables custom scheduler, arbitration and application ports DOWNLOAD DATASHEET |
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| DDR3/2 Protocol Controller | Low latency, area efficient digital interface between a single on-chip interface and a DDR3/2 PHY. Enables custom scheduler, arbitration and application ports DOWNLOAD DATASHEET |
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| DDR2/DDR Memory Controller | Efficient digital interface between up to 32 on-chip application buses and a DDR2/DDR PHY. Provides QoS, arbitration and optimized memory transactions DOWNLOAD DATASHEET |
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| DDR2/3-Lite Memory Controller | Efficient digital interface between up to 32 on-chip application buses and a DDR2/3-Lite/mDDR or DDR2/3-Lite or DDR2/DDR PHY. Provides QoS, arbitration and optimized memory transactions DOWNLOAD DATASHEET |
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| DDR multiPHY | Supports a broad range of DDR SDRAM types such as LPDDR2, LPDDR, Mobile DDR, DDR3/3L/3U and DDR2 supporting speeds up to 1066Mbps. DOWNLOAD DATASHEET |
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| DDR3/2 PHY | Operates at up to 2133 Mbps and offers a wealth of in-system calibration capabilities to ease implementation of the interface at higher data rates |
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| DDR2/3-Lite/mDDR SDRAM PHY | Area and feature-optimized IP solution operating at up to 1066 Mbps using Mobile DDR, DDR2 or DDR3 SDRAMs DOWNLOAD DATASHEET |
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| DDR2/DDR PHY | Operates at speeds up to 1066 Mbps and is available in leading 130nm, 90nm and 65nm process technologies DOWNLOAD DATASHEET |
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| Intelli DDR IP | Memory controllers, PHY and DLL solutions and memory models |
- Ethernet
| Comprehensive Ethernet 10/100/1G/10G IP Solutions | more |
| Ethernet Quality-of-Service | Compliant with the IEEE 802.3-2005 standard and supports the IEEE 1588-2002, IEEE 1588-2008 and IEEE AVB specifications |
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| Ethernet Complete Solution | Complete Ethernet IP solution including digital cores, PHY IP and verification IP. DOWNLOAD DATASHEET |
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| 10/100/1G | Compliant with IEEE 802.3-2002, 802.1Q, and 1588-2002 specifications with checksum engine offload engine and AMD Magic packet support. DOWNLOAD DATASHEET |
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| 10/100 | Compliant with IEEE 802.3-2002, 802.1Q, and 1588-2002 specifications with checksum engine offload engine and AMD Magic packet support. DOWNLOAD DATASHEET |
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| 1G/2.5G/10G | Compliant with the IEEE 802.3ae, IEEE 802.3x with configurable RMON/MIB counters and an optional MDIO interface as part of a full 10G solution. DOWNLOAD DATASHEET |
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| Ethernet PCS | Implements the PCS layer of the 10 Gigabit Ethernet Extended Sub-layer (XGXS) as described in the IEEE 802.3ae specification.< DOWNLOAD DATASHEET |
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| Verification IP | The DesignWare Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to- PHY layer interfaces. DOWNLOAD DATASHEET |
- HDMI
| Silicon-proven HDMI 1.4 and 1.3 TX & RX solution: Controller and PHY | more |
| HDMI 1.4 Transmitter (TX) | The HDMI 1.4 TX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through and HDMI interface. DOWNLOAD DATASHEET |
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| HDMI 1.4 Receiver (RX) | The HDMI 1.4 RX interface compromises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface. DOWNLOAD DATASHEET |
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| HDMI 1.3 Transmitter (TX) | The HDMI 1.3 TX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface. DOWNLOAD DATASHEET |
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| HDMI 1.3 Receiver (RX) | The HDMI 1.3 RX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface. DOWNLOAD DATASHEET |
- JPEG
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Multimedia IP solution for image compression and decompression | more |
| | The CODEC encodes and decodes still or motion image data of up to four color components, according to the JPEG baseline algorithm as specified in the ISO/IEC 10918-1 standard. DOWNLOAD DATASHEET |
- MIPI
| 3G DigRF, CSI-2 and D-PHY IP solutions for the MIPI interface | more |
| 4G DigRF |
Area, power and pin count efficient interface for advanced LTE and Mobile WiMax Baseband SoCs and RFICs |
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| 3G DigRF | Controllers and PHYs for MIPI DigRF V3 standard interface |
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| CSI-2 |
Synthesizable controller for MIPI CSI-2 Host application |
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| D-PHY |
Physical Layer for MIPI CSI-2, DSI and UniPro standard interfaces |
| | Supports the SD 2.00, SDIO 1.1, MMC 4.2 and CE-ATA 1.1 specification. The IP is optimized for low power, high performance storage devices DOWNLOAD DATASHEET |
- PCI Express
| Complete, silicon-proven PCI Express 3.0, 2.0 and 1.1 IP solutions | more |
| PCIe Complete Solution | Complete PCIe IP solution consisting of digital cores, PHY IP and Verification IP for PCIe 3.0, 2.0 and 1.1. DOWNLOAD DATASHEET |
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| Endpoint | Implements the port logic required for a PCIe Endpoint and it is compliant with the PCI Express 3.0, 2.0, 1.1 and PCI-SIG SR-IOV specifications DOWNLOAD DATASHEET |
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| Root Port | Implements the port logic required for a PCIe Root Complex and it is compliant with the PCI Express 3.0, 2.0 and 1.1 specifications. DOWNLOAD DATASHEET |
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| Dual Mode | Implements the port logic required for both a PCIe Root Complex and Endpoint and it is compliant with the PCIe 3.0, 2.0, 1.1 and PCI-SIG SR-IOV specifications. DOWNLOAD DATASHEET |
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| Switch Port | Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and it is compliant with the PCI Express 3.0, 2.0 and 1.1 specifications. DOWNLOAD DATASHEET |
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| PCIe to AHB Bridge | Allows the DesignWare PCI Express port logic to bridge to be the AMBA 2.0 AHB on-chip bus DOWNLOAD DATASHEET |
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| PCIe to AXI Bridge | Allows the DesignWare PCI Express port logic to bridge to be the AMBA 3 AXI on-chip bus DOWNLOAD DATASHEET |
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| 1.1 PHY | The low power PHY integrates high-speed mixed-signal custom CMOS circuitry The IP is compliant with the PCIe 1.1 specification and PIPE interface standard. DOWNLOAD DATASHEET |
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| 2.0 PHY | The low power PHY integrates high-speed mixed-signal custom CMOS circuitry. The IP is compliant with the PCIe 2.0 specification and PIPE interface standard DOWNLOAD DATASHEET |
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| 3.0 PHY | Compliant with the PCI Express 3.0 (8.0 GT/s), 2.0 (5.0 GT/s) and 1.1 (2.5 GT/s) specifications DOWNLOAD DATASHEET |
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| Verification IP | DesignWare Verification IP can be configured for verification at multiple levels including the 8b/10b and PIPE interfaces. It can verify both the MAC and PHY. DOWNLOAD DATASHEET |
| PCI | The PCI IP supports 32-bit or 64-bit bus paths on either the PCI bus or the application interface and is compliant with the PCI 2.3 specification. DOWNLOAD DATASHEET |
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| PCI-X | The IP supports 32-bit or 64-bit PCI-X bus paths and is compliant with the PCI-X 2.0 (mode1) also know as 1.0a and the PCI 2.3 specifications. DOWNLOAD DATASHEET |
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| Verification IP | DesignWare Verification IP helps to create a virtual PCI or PCI-X system around the design, enabling quick and efficient generation of tests. DOWNLOAD DATASHEET |
- SATA
| Complete, interoperable SATA IP Solution: Device, Host, PHY, VIP | more |
- USB
| Complete, silicon-proven USB IP solution: controller, PHY and VIP | more |
| USB Complete Solution | Complete USB IP solution including controllers, PHY IP and Verificaiton IP for SuperSpeed USB, USB 2.0, LPM-HSIC and more. DOWNLOAD DATASHEET |
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| SuperSpeed USB | The DesignWare® SuperSpeed USB IP complete solution is based on the USB 3.0 specification from the USB Implementers Forum and consists of the device controller, PHY and verification IP. |
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| USB 2.0 LPM-HSIC | Implements a new power sleep state which reduces power consumption, by providing faster suspend and resume times by three orders of magnitude. DOWNLOAD DATASHEET |
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| USB 2.0 HS OTG | The IP performs as a standard Hi-Speed Dual-Role Device (DRD), operating as either a USB 2.0 compliant peripheral or a USB 2.0 host DOWNLOAD DATASHEET |
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| USB 2.0 EHCI Host | Compliant with the specifications for the USB 2.0 Enhanced Host Controller Interface (EHCI) and the USB 1.1 Open Host Controller Interface (OHCI) 1.0 DOWNLOAD DATASHEET |
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| USB 2.0 Device | Compliant to the USB 2.0 specification. The IP supports high-speed (480-Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) devices and USB 2.0 UTMI DOWNLOAD DATASHEET |
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| USB 2.0 picoPHY | The USB 2.0 picoPHY supports the Battery Charging v1.1 and OTG 2.0 specifications, and is designed for low power and small area DOWNLOAD DATASHEET |
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| USB 2.0 nanoPHY | Compliant to the USB 2.0 specification. The USB 2.0 nanoPHY is targeted to leading 45nm, 65nm, 90nm, and 130nm low power CMOS digital logic processes. DOWNLOAD DATASHEET |
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| USB 2.0 LPM-HSIC PHY | Compliant to the USB 2.0 specification. The IP supports 1.2V LVCMOS signaling with integrated PHY including transmitter, receiver, digital core, ESD & 480 Hz PLL DOWNLOAD DATASHEET |
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| USB 2.0 HS OTG PHY | Compliant to the USB 2.0 specification .The PHY IP includes all the required logical, geometric, & physical design files to implement USB 2.0 OTG capabilities |
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| USB 1.1 Host | The USB 1.1 Host is compliant with the USB 1.1 specification. The IP supports full and low speeds and is compatible with USB 2.0 & Open HCI 1.0 specifications. DOWNLOAD DATASHEET |
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| USB 1.1 Device | The USB 1.1 Device is compliant with USB 1.1 specification. The IP supports full and low speeds devices. |
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| USB 1.1 Hub | The USB 1.1 Hub is compliant with USB 1.1 specification. The IP supports low-speed and full speed devices on downstream ports DOWNLOAD DATASHEET |
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| Verification IP | DesignWare Verification IP can be configured as a host or dual role device. The flexible programming with protocol checking verifies the USB host, hub or device DOWNLOAD DATASHEET |
- XAUI
| XAUI PHY supporting the 10 Gigabit Ethernet standards | more |
| | Supports a wide range of configurations including 1.0v & 1.2v core supplies and 2.5v & 3.3v I/O supplies. The PHY also supports the IEEE 802.3ae specification DOWNLOAD DATASHEET |
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