| Manufacturing-Aware Routing at 32/28nm |
Considering yield as one of the objectives during design has become a necessity at the 32/28nm node. In this webinar, you will learn techniques for addressing manufacturing during routing with IC Compiler’s Zroute technology which considers manufacturability as a routing objective.
Dr. Tong Gao, Synopsys Fellow, Synopsys; Yukti Rao, Product Marketing Manager, Synopsys
Aug 11, 2010 |
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| Realizing Today’s 32nm and Beyond Large Capacity Designs |
Synopsys Design Planning R&D will highlight the latest hierarchical design exploration and planning technology available in IC Compiler for handling today’s large 32/28nm designs.
Thomas Andersen, Director of R&D, IC Compiler, Synopsys; Mark Bollar, Director of Product Marketing, IC Compiler, Synopsys
Jul 28, 2010 |
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| Faster ECO Fixing Flows with PrimeTime and IC Compiler |
This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010 |
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| IC Compiler Ecosystem |
There is a thriving ecosystem around IC Compiler and the Galaxy Implementation Platform products engineered to work together to speed design closure. Hear from designers who share how they have relied on the IC Compiler ecosystem to achieve faster time to results and improved productivity.
JC Lin, Synopsys
Oct 31, 2009 |
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| Faster Power/Ground Grid Closure with In-Design Rail Analysis |
Join our experts to learn how you can use In-Design Rail Analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, helping you accelerate the path to final design closure.
Tom Chau, Group CAE Director, Synopsys; Dr. Henry Sheng, R&D Group Director, Synopsys
Jun 25, 2009 |
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| Faster Design Closure with Congestion Minimization |
This webinar will show you how predictable routing congestion from synthesis to tapeout eliminates unnecessary iterations, speeding up your overall turnaround time.
Janet Olson, Synopsys
Jun 09, 2009 |
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| In-Design PV for Faster Time-to-Tapeout |
Synopsys’ physical design and verification technologists will show you how in-design physical verification combines timing awareness and signoff accuracy to speed up your tapeout schedule.
Kerstin McKay, CAE Director, Physical Verification products, Synopsys
May 20, 2009 |
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| Accelerating Time-to-SI Closure |
View this webinar to learn how to use signoff-driven SI-closure to keep your schedule on track and your performance on target.
Dr. Henry Sheng, Synopsys; Dr. Jinan Lou, Synopsys
Mar 31, 2009 |
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