DATE 2010
March 8-12, 2010
International Congress Centre (ICC)
Dresden, Germany
Monday, March 8
Tutorial D: Chip-Package Co-Design Challenges for 3D Integration
9:30-18:00
Room: Konferenz 1
Speaker: Terry Ma, Vice President Engineering
This tutorial will review new 3D integration technologies and their impact on chip-package co-design. In the morning, the tutorial will highlight the continuing needs for higher levels of integration and the mandates imposed by the stringent cost- and power constraints. The presenters will address the many benefits but also challenges 3D chip-stacking introduces and suggest methods to adopt the design of dies and advanced packages to higher levels of integration. In addition to new EDA tools and flows, our industry is adopting a new design practice: physical design prototyping of chip stacks. Several experts from industry and academia will share their experience and offer advice before the lunch break. In the early afternoon session a representative from academia and two major EDA vendors will talk about the multi-physics challenges that need to be considered, both in new EDA flows and the physical design prototyping, to assure success. Finally, two talks providing an outlook of how 3D technologies impact current and future products will summarize and end the day.
Tutorial E2: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices
14:30-18:00
Room: Konferenz 3
Speaker: Rohit Kapur, Synopsys Scientist
The push for portable, battery-operated, and "cool-and-green" electronics has elevated power consumption as the defining metric of integrated circuit (IC) design. Testing ICs built for such applications requires judicious consideration of test power implications on various aspects of the design cycle (e.g., packaging and power grid design), test engineering (multi-site ATE power supply limitations and board design), power-aware test planning (DFT and ATPG), and developing the enabling EDA tool infrastructure (SW for estimation, reduction and low-power test generation). Furthermore, with power optimization and power management techniques becoming "de-facto" in almost all emerging 45nm and lower chips, systematic testing of these structures and the device in the presence of these structures becomes mandatory. This tutorial is intended to provide an in-depth and up-to-date understanding of low-power IC testing covering (a) dimensions of power-aware testing, (b) techniques for estimation and reduction of test power consumption and (c) test of power managed designs. Case-studies illustrating industrial design deployment practices and existing EDA vendor support will be outlined to illustrate capabilities and gaps in the state-of-the-art.
This tutorial is part of the annual IEEE Computer Society TTTC Test Technology Educational Program (TTEP.)
Tuesday, March 9
2.1 EXECUTIVE SESSION: How to Address Today’s Growing System Complexity?
11:30-13:00
Room: Saal 5 (ground floor)
Executive: Antun Domic, Sr. Vice President and General Manager
The widening gap between growing system complexity and designer productivity increasingly limits traditional design tools, methods and flows. This results in several new approaches that work to elevate the limitations of different aspects of system design. Executives from the IC value chain will present the technical and business challenges and the new opportunities in designing today’s complex systems.
2.8 PANEL SESSION: Are we there yet? Has System Assembly from IP Blocks Become Like Connecting LEGO Blocks?
11:30-13:00
Room: Exhibition Theatre
Panelist: Joachim Kunkel, Vice President and General Manager
This panel will explore the trends in IP re-use and discuss where IP blocks end and systems start. Furthermore, it will also explore the trends in IP-reuse and assembly, assess the state of the art of IP assembly and co-simulation standards like IP-XACT and OSCI TLM-2.0. Starting from IP assembly approaches at the RT-level, the panel will chart the direction where IP assembly will go from here towards re-use and assembly at the transaction level.
Wednesday, March 10
Hands-on Workshop: Enhancing Verification Efficiency Using Virtualization Register Now!
9:00-13:00
Room: Seminar Room 3
Verification is known to strongly influence project efforts and timelines. Also, software has an increasing impact on project success. As a result, smart verification taking into account embedded software becomes more and more important. Using virtualization of embedded hardware, verification efficiency can be improved in two ways: (1) bottom up, incrementally augmenting traditional RTL verification with virtualized transaction-level models of processors and peripherals, as well as (2) top down, starting with virtual platforms originally intended for early pre-silicon software development. This workshop will address both concepts in detail, featuring examples and demonstrations. Participants will learn about the role of transaction- level models, best practices of using virtualization and selecting the right prototyping approach. Register Now!
7.8 PANEL SESSION: Who is Closing the Embedded Software Design Gap?
14:30-16:00
Room: Exhibition Theatre
Speaker: Pierre Bricaud, R&D Director
As pointed out in the ITRS roadmap, the level of embedded software complexity is greater than the pure HW complexity of SoCs when comparing, for example, lines of HDL and C code. Even worse, SW complexity grows faster than HW complexity (Moore’s Law) and SW productivity increases more slowly than HW productivity. A new design gap - the gap of embedded software – has appeared. EDA has now identified ESL as a field with sufficient revenue and revenue growth, but do they really approach the SW productivity challenge?
This panel gives the answer by presenting recent EDS products and solutions in the area of ESW, contrasting them with needs of industry, and discussing ways out of the ESL productivity crisis.
Thursday, March 11
10.2 PANEL SESSION: First Commandment: At Least Do Nothing Well
11:00-12:30
Room: Konferenz 6
Panelist: Antun Domic, Sr. Vice President and General Manager
In a recent keynote speech, UCB Prof. Randy Katz defined power as the 21st century's most limited, as well as most wasted resource: not only we seem to be unable to generate "greener" power but, at all levels, we seem to be really poor even in making an efficient use of our precious power. We waste while doing things, as well as while doing nothing! "Electronics is sized for peak power consumption, and designed for continuous activity.
Friday, March 12
W5 3D Integration Workshop
Session 3: Paper: An Analytical Study on the Role of Thermal TSVs in a 3D-IC Chip Stack
11:00-11:30
Room: Konferenz 6
Speakers: Min Ni, Qing Su, Zongwu Tang and Jamil Kawa, R&D Team
Session 6: Panel Discussion: "3D: A Reality?"
15:00-16:00
Room: Konferenz 6
Panelist: Rajiv Maheshwary, Sr. Director